RP/0/RP0/CPU0:R4#show isis trace all | include UPD_LSP_SET_SRM | utility tail -n 60 Wed Sep 16 23:25:42.387 UTC Sep 16 23:18:59.104 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: Timer L2 0040.0400.4004.00-00 Sep 16 23:19:08.491 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: Timer L2 0040.0400.4004.00-00 Sep 16 23:19:09.943 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: None L2 0040.0400.4004.00-00 Sep 16 23:19:12.042 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: Timer L2 0040.0400.4004.00-00 Sep 16 23:19:15.006 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1252 UPD_LSP_SET_SRM Upd Type: Timer L2 0040.0400.4004.00-00 Gi0/0/0/1 Sep 16 23:19:15.006 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: Timer L2 0040.0400.4004.00-00 Sep 16 23:19:16.902 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1252 UPD_LSP_SET_SRM Upd Type: Timer L2 0040.0400.4004.00-00 Gi0/0/0/1 Sep 16 23:19:16.902 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: Timer L2 0040.0400.4004.00-00 Sep 16 23:19:16.942 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: LSP L2 0030.0300.3003.01-00 Sep 16 23:19:17.692 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: LSP L2 0010.0100.1001.00-00 Sep 16 23:19:18.513 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: LSP L2 0030.0300.3003.01-00 Sep 16 23:19:18.696 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: LSP L2 0020.0200.2002.00-00 Sep 16 23:19:18.696 isis/1/upd 0/RP0/CPU0 t4509 isis_upd_lsp_set_all_srm:1273 UPD_LSP_SET_SRM Upd Type: LSP L2 0030.0300.3003.00-00