RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 11:28:07.561 UTC
11:28:07.648 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R2#logmsg informational STEP11-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 11:28:07.716 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#logmsg informational STEP11-CLEAR: clear counters GigabitEthernet0/0/0/1
Sun Sep 20 11:28:07.841 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/1
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 11:28:07.942 UTC
11:28:08.011 UTC Sun Sep 20 2026