RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:16:45.951 UTC
10:16:46.045 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R2#logmsg informational STEP1-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:16:46.150 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#logmsg informational STEP1-CLEAR: clear counters GigabitEthernet0/0/0/1
Sun Sep 20 10:16:46.349 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/1
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:16:46.512 UTC
10:16:46.553 UTC Sun Sep 20 2026