RP/0/RP0/CPU0:R1#show clock
Sun Sep 20 10:24:58.132 UTC
10:24:58.181 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R1#logmsg informational STEP2-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:24:58.260 UTC
RP/0/RP0/CPU0:R1#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R1#show clock
Sun Sep 20 10:24:58.439 UTC
10:24:58.476 UTC Sun Sep 20 2026