RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:25:02.119 UTC
10:25:02.214 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R2#logmsg informational STEP2-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:25:02.320 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#logmsg informational STEP2-CLEAR: clear counters GigabitEthernet0/0/0/1
Sun Sep 20 10:25:02.484 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/1
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:25:02.613 UTC
10:25:02.709 UTC Sun Sep 20 2026