RP/0/RP0/CPU0:R1#show clock
Sun Sep 20 10:41:13.124 UTC
10:41:13.164 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R1#logmsg informational STEP4-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:41:13.275 UTC
RP/0/RP0/CPU0:R1#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R1#show clock
Sun Sep 20 10:41:13.411 UTC
10:41:13.452 UTC Sun Sep 20 2026