RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:41:16.790 UTC
10:41:16.841 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R2#logmsg informational STEP4-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:41:16.924 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#logmsg informational STEP4-CLEAR: clear counters GigabitEthernet0/0/0/1
Sun Sep 20 10:41:17.115 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/1
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:41:17.309 UTC
10:41:17.351 UTC Sun Sep 20 2026