RP/0/RP0/CPU0:R1#show clock
Sun Sep 20 10:48:35.530 UTC
10:48:35.571 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R1#logmsg informational STEP5-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:48:35.676 UTC
RP/0/RP0/CPU0:R1#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R1#show clock
Sun Sep 20 10:48:35.857 UTC
10:48:35.899 UTC Sun Sep 20 2026