RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:48:39.220 UTC
10:48:39.261 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R2#logmsg informational STEP5-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:48:39.364 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#logmsg informational STEP5-CLEAR: clear counters GigabitEthernet0/0/0/1
Sun Sep 20 10:48:39.507 UTC
RP/0/RP0/CPU0:R2#clear counters GigabitEthernet0/0/0/1
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R2#show clock
Sun Sep 20 10:48:39.699 UTC
10:48:39.742 UTC Sun Sep 20 2026