RP/0/RP0/CPU0:R3#show clock
Sun Sep 20 10:48:43.147 UTC
10:48:43.264 UTC Sun Sep 20 2026
RP/0/RP0/CPU0:R3#logmsg informational STEP5-CLEAR: clear counters GigabitEthernet0/0/0/0
Sun Sep 20 10:48:43.485 UTC
RP/0/RP0/CPU0:R3#clear counters GigabitEthernet0/0/0/0
                                ^
% Invalid input detected at '^' marker.
RP/0/RP0/CPU0:R3#show clock
Sun Sep 20 10:48:43.665 UTC
10:48:43.704 UTC Sun Sep 20 2026